Final Exam, ECE 448- Spring 2022, UIC Name:
\nPage 1 of 4
\nFinal Exam, ECE 448 Transistors – Spring 2022
\nUniversity of Illinois at Chicago
\n10:30 am to 12:30 pm on May 03, 2022
\nName: UIN:
\n[30 points] PROBLEM # 1
\nAssume a hypothetical pn junction with the doping profile shown below, derive the
\nexpression for the depletion width and the electric field under equilibrium conditions (Note
\n\u201ca\u201d is negative)
\nFinal Exam, ECE 448- Spring 2022, UIC Name:
\nPage 2 of 4
\n[30 points] PROBLEM # 2
\nIn a silicon MOS capacitor with an n-type substrate and a p + polysilicon gate (Ef = Ev),
\nthe substrate doping is uniform with Nd = 2 \u00d7 1018 cm\u22123. The oxide thickness is 3 nm. There
\nis a p + channel contact biased at -1V relative to the substrate. The voltage drop across the
\noxide is Vox = \u22120.6 V.
\n(a) Determine the state of the channel region (accumulation, flat-band, depletion, strong
\ninversion, etc.).
\n(b) Determine the applied gate voltage.
\n(c) Sketch the charge density, electric field and energy band diagram for the system.
\nFinal Exam, ECE 448- Spring 2022, UIC Name:
\nPage 3 of 4
\n[20 points] PROBLEM # 3
\nCalculate the base transit time in a npn transistor with NDE= 1019 cm-3
\n, NAB = 1017 cm-3
\n, VBE=
\n0.8V and a neutral basewidth W = 0.8 \u03bcm. Assume DnB= 18 cm2 s-1 and independent of position.
\nFinal Exam, ECE 448- Spring 2022, UIC Name:
\nPage 4 of 4
\n[20 points] PROBLEM # 4
\nList the steps needed for fabricating an n-MOSFET device. Draw figures to illustrate your
\nresponse clearly.<\/p>\n
—–<\/p>\n
ECE 448 Final Exam, Spring 2022, UIC Name: Page 1 of 4
\nECE 448 Transistors Final Exam – Spring 2022
\nChicago’s University of Illinois
\nOn May 3, 2022, from 10:30 a.m. to 12:30 p.m.
\n[30 points] Name: UIN: PROBLEM #1 Assume a hypothetical pn junction with the doping profile shown below, and calculate the depletion width and electric field under equilibrium conditions (Note: “a” is negative).
\nECE 448 Final Exam, Spring 2022, UIC Name: Page 2 of 4 [30 points] PROBLEM # 2 The substrate doping in a silicon MOS capacitor with an n-type substrate and a p + polysilicon gate (Ef = Ev) is uniform, with Nd = 2 1018 cm3. The thickness of the oxide is 3 nm. A p + channel contact is biased at -1V.<\/p>\n","protected":false},"excerpt":{"rendered":"
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